Standard cells are a well-established technology for constructing integrated circuits (ICs), especially ICs that contain significant random logic sections, such as system-on-a-chip (SoC) ICs. See S. Saika, “Standard cell library and semiconductor integrated circuit,” U.S. Pat. No. 8,302,057 B2 (incorporated by reference herein), J. J. Lee, et al., “Standard Cell Placement Technique For Double Patterning Technology,” U.S. Pat. Applic. No. 20130036397 A1 (also incorporated by reference herein), D. D. Sherlekar, “Power Routing in Standard Cell Designs,” U.S. Pat. Applic. No. 20120249182 A1 (also incorporated by reference herein), H. H. Nguyen, et al., “7-tracks standard cell library,” U.S. Pat. No. 6,938,226 (also incorporated by reference herein), P. Penzes, et al., “High-speed low-leakage-power standard cell library,” U.S. Pat. No. 8,079,008 (also incorporated by reference herein), H.-Y. Kim, et al., “Standard cell libraries and integrated circuit including standard cells,” U.S. Pat. No. 8,174,052 (also incorporated by reference herein), and O. M. K. Law, et al., “Standard cell architecture and methods with variable design rules,” U.S. Pat. No. 8,173,491 (also incorporated herein by reference) for examples of known standard-cell techniques.
As IC feature sizes continue to shrink, difficult-to-predict side effects of lithography and other fabrication processes have challenged the traditional standard cell model. At feature sizes of 28 nm, 22 nm and below, various restrictions—including new “design rules” and unpredictable interactions between features over longer relative distances—combine to create an environment in which traditional “scaling” of existing libraries to meet new design rules produces unacceptable manufacturing yields, unacceptable area efficiency, or both.
One approach to address these problems has been to impose additional “regularity” restrictions (i.e., restrictions beyond mere design rules) on the IC layouts. See, e.g., V. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, A. J. Strojwas, and L. Pileggi. “Design methodology for IC manufacturability based on regular logic-bricks,” DAC'05, pages 353-358; T. Jhaveri, V. Rovner, L. Liebmann, L. Pileggi, A. J. Strojwas, and J. D. Hibbeler, “Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(4):509-527, April 2010. Such restricted design approaches have been employed, for example, in U.S. Pat. No. 8,004,315 (“Process for making and designing an IC with pattern controlled layout regions”) to Jhaveri, U.S. Pat. Applic. No. 20080137051 (“Lithography and Associated Methods, Devices, and Systems”) to Maly, and U.S. Pat. Applic. No. 20100001321 (“Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions”) to Becker et al.
While the restricted approach can be usefully employed and can be effective in addressing the yield impact of unpredictable interactions in deep submicron processes, there remain certain commercially important applications on which restricted approaches can fall short. A prime example involves standard cell libraries. Such libraries typically include a large number (e.g., hundreds) of cells, including many that implement small logic functions. Implementing such libraries directly (i.e., with support for every cell) using restricted approaches typically leads to poor area efficiency. On the other hand, because the users of such libraries (e.g., fabless chip makers) often have large infrastructure investments (e.g., CAD systems, large collections of macro blocks) that depend on the features of particular libraries, there remains a significant need for translation or adaption of existing standard cell libraries to deep submicron processes in a way that avoids and/or reduces the unpredictable effects that can substantially diminish the yield of otherwise design-rule-clean cell libraries. The present invention addresses this, as well as other, needs.